Recently, the development has been advancing at a high pitch for a hetero bipolar transistor (HBT) that realizes an operation at a high frequency region with better conduction characteristics conferred by incorporating a hetero junction structure, such as Si/SiGe and Si/SiC, into a bipolar transistor fabricated on a silicon substrate. The HBT uses an Si/SiGe hetero junction structure obtained by allowing epitaxial growth of an SiGe layer on an Si substrate, so that it realizes a transistor operating at a high frequency region at which a conventional transistor cannot operate unless it uses a compound semiconductor substrate, such as GaAs. The HBT is made of materials having a good affinity for a general silicon process, such as an Si substrate and an SiGe layer, which provides remarkable advantages in achieving high integration and a low cost. In particular, integrating an SBT and a MOS transistor (MOSFET) by forming the both on a common Si substrate makes it possible to fabricate a high-performance BiCMOS device. Moreover, the BiCMOS device is expected to serve as a system LSI applicable to communication systems.
FIG. 10 is a cross section showing a structure of a conventional HBT. As is shown in the drawing, a top portion of an Si substrate 500 having a (001) plane forms a retrograde well 501 with a depth of 1 μm including an N-type impurity, such as phosphorous, introduced by the epitaxial growth method, ion implantation method, etc. Also, for the isolation, provided are a shallow trench 503 filled with silicon oxide and a deep trench 504 formed from an undoped polysilicon film 505 and a silicon dioxide film 506 surrounding the same. The trenches 503 and 504 have depths of approximately 0.35 μm and 2 μm, respectively.
Also, a collector layer 502 is provided in the Si substrate 500 at a region sandwiched by the trenches 503, and an N+ collector connecting layer 507 is provided in the Si substrate 500 at a region separated from the collector layer 502 by the shallow trench 503 for establishing a contact with an electrode of the collector layer 502 through the retrograde well 501.
Also, a first deposited oxide film 508 with a thickness of approximately 30 nm having a collector opening portion 510 is formed on the Si substrate 500, and an Si/Si1-xGex layer 511 is formed by depositing an Si1-xGex layer doped with a P-type impurity with a thickness of approximately 60 nm and an Si film with a thickness of approximately 10 nm on the top surface of the Si substrate 500 at a portion exposed to the collector opening portion 510. The bottom portion of the Si/Si1-xGex layer 511 at the center thereof (a region below a base opening portion 518, which will be described below) functions as an intrinsic base 519. On the other hand, the top portion of the Si/Si1-xGex layer 511 at the center thereof functions as an emitter layer.
A second deposited oxide film 512 with a thickness of approximately 30 nm to serve as an etch stopper is provided on the Si/Si1-xGex layer 511 and the first deposited oxide film 508, and the second deposited oxide film 512 is provided with a base junction opening portion 514 and a base opening portion 518. Provided next are a P+ polysilicon layer 515 with a thickness of approximately 150 nm that fills in the base junction opening portion 514 and extends over the second deposited oxide film 512, and a third deposited oxide film 517. An extrinsic base 516 is constructed by the Si/Si1-xGex layer 511 except for the region below the base opening portion 518 and the P+ polysilicon layer 515.
Also, the P+ polysilicon layer 515 and the third deposited oxide film 517 are opened at portions positioned above the base opening portion 518 in the second deposited oxide film 512, and a fourth deposited oxide film 520 with a thickness of approximately 30 nm is formed on the side surface of the P+ polysilicon layer 515. Further, a sidewall 521 made of polysilicon with a thickness of approximately 100 nm is provided on the fourth deposited oxide film 520. Then, an N+ polysilicon layer 529 is provided to fill the base opening portion 518 and to extend over the third deposited oxide film 517, and the N+ polysilicon layer 529 thus functions as an emitter connecting electrode. The fourth deposited oxide film 520 not only electrically isolates the P+ polysilicon layer 515 from the N+ polysilicon layer 529, but also prevents out-diffusion of the impurity from the P+ polysilicon layer 515 into the N+ polysilicon layer 529. Also, the third deposited oxide film 517 electrically isolates the top surface of the P+ polysilicon layer 515 from the N+ polysilicon layer 529.
Further, a Ti silicide layer 524 is formed on the surfaces of the collector connecting layer 507, P+ polysilicon layer 515, and N+ polysilicon layer 529, and the outside sidewalls of the N+ polysilicon layer 529 and the P+ polysilicon layer 515 are covered with a sidewall 523. The entire substrate is covered with an inter-layer insulator film 525, through which contact holes that respectively reach the Ti silicide layer 524 formed on the N+ collector connecting layer 507, P+ polysilicon layer 515 as a part of the extrinsic base, and N+ polysilicon layer 529 functioning as the emitter connecting electrode are provided. Then, each contact hole is filled with a W plug 526 and is provided with a metal wiring 527 connected to the W plug 526 and extending over the inter-layer insulator film 525.
Problems to be Solved
However, the above-discussed conventional HBT or SiGe-BiCMOS has problems as follows.
FIG. 11(a) is a view showing dependencies of a base current and a collector current on a base-emitter voltage, that is, so-called Gummel characteristics of the conventional HBT. In the drawing, the horizontal axis represents the base-emitter voltage (V), and the vertical axis represents the base current or collector current (A) (logarithmic scales). As is shown in the drawing, the parallel relation between the collector current characteristics curve and the base current characteristics curve is lost at a low base-emitter voltage region, and there is an excessive base current. In short, there is an inconvenience that the linearity of the current characteristics is deteriorated in the low bias region of the HBT.
Causes of such an inconvenience are checked, and one of the causes is found to be a recombination current generated excessively at a region underneath the second deposited oxide film 112 in the Si layer. It is assumed that such an excessive recombination current is generated because a depletion layer at the pn junction region in the Si layer is not formed in a satisfactory shape.
FIGS. 12(a) and 12(b) are an enlarged partial cross section showing an emitter-base junction region in the conventional HBT, and a doping profile of boron along a cross section in the vicinity of the emitter-base junction region, respectively. As shown in FIG. 12(a), the Si/Si1-xGex layer 511 is formed by sequentially depositing an undoped SiGe spacer layer 551 with a Ge content of 15%, a P-type graded SiGe base layer 552 including boron at a high concentration with a Ge content continuously changing from 15% at the lower end to 0% at the upper end, and an undoped Si-cap layer 553. The Si-cap layer 553 is provided with an N-type emitter diffusion layer 553a formed by introducing phosphorous out-diffused from the N+ polysilicon layer 529 (emitter connecting electrode) at a high concentration at a region directly below the base opening portion 518 and in contact with the N+ polysilicon layer 529. Then, a peripheral layer 553b (especially, the bottom portion) of the Si-cap layer 511 surrounding the emitter diffusion layer 553a includes boron out-diffused from the graded SiGe layer 552, which makes the peripheral layer 553b into the P-type. Hence, there is a pn junction region between the emitter diffusion layer 553a and the peripheral layer 553b in the Si-cap layer 551, and a depletion layer 554 expands along the both sides of the metallurgical pn junction interface in the pn junction region. At this point, the depletion layer 554 has a broader width in the upper part of the Si-cap layer 551. Hence, a recombination current generated from carriers recombined within the depletion layer 554 increases, which is assumed to cause deterioration in the linearity of the current characteristics as shown in FIG. 11(a).
According to Physics of Semiconductor Devices, S. M. Sze, John Wiley & Sons, Inc., 1981, pp. 89-94, the recombination current Irec is expressed as:Irec=S∫q·U·dx (x=0 to W),where S is the area of the pn junction, w is the depletion layer width, U is a recombination rate, and q is the elemental charge.
Here, the recombination rate U is determined by parameters of deep level traps in the depletion layer, such as densities at deep level traps, depths of the levels of the traps, the capture cross sections of the traps, and so on. The above expression indicates that a recombination current increases as the width of the depletion layer (a distance from the first depletion layer end to the second depletion layer end) broadens, because deep level traps in the depletion region between a first depletion layer edge and a second depletion layer edge in FIG. 12(a) work as recombination centers.
In other words, as shown in FIG. 12(a), according to the conventional bipolar transistor discussed above, it is assumed that the recombination current Irec increases because the depletion region 554 becomes wider particularly in the upper part of the Si-cap layer 551.
In view of the foregoing, the present invention has an object to provide a bipolar transistor having a satisfactory linearity of the current characteristics and a fabrication method thereof by taking a means to improve a doping profile of an impurity in the Si-cap layer in the HBT.